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gf180mcu_fd_sc_mcu9t5v0__and2_1

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gf180mcu standard-cell layout `gf180mcu_fd_sc_mcu9t5v0__and2_1` from the #4 test corpus.

Schematic

Schematic diagram of gf180mcu_fd_sc_mcu9t5v0__and2_1

Drawn from PDK netlist `gf180mcu_fd_sc_mcu9t5v0__and2_1.cdl` @ commit `3781fd29` (google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0), sha256 `c4a48feea59b…436d25`. NAND2 + output inverter, 6 physical devices, 1:1 with this diagram (no folding) — verified device-by-device in issue #1123's PR body.

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Metrics

Layers13
Cells1
Instances0

Signals

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typical/5.000V/27C

  • tphl181.88 ps
  • tplh176.15 ps

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