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gf180mcu_fd_sc_mcu9t5v0__dffnq_1

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gf180mcu standard-cell layout `gf180mcu_fd_sc_mcu9t5v0__dffnq_1` from the #4 test corpus.

Schematic

Schematic diagram of gf180mcu_fd_sc_mcu9t5v0__dffnq_1

Drawn from PDK netlist `gf180mcu_fd_sc_mcu9t5v0__dffnq_1.cdl` @ commit `3781fd29` (google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0), sha256 `bff973c552b4…6259c9`. Transmission-gate master-slave D flip-flop (24 physical devices, structurally identical to sky130's dfxtp_2 minus its doubled output stage), presented as a functional block diagram — every device fully traced by gate/drain/source connectivity into its functional block in issue #1123's PR body.

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Metrics

Layers13
Cells1
Instances0

Signals

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typical/5.000V/27C

  • tcq402.14 ps

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