sky130_fd_sc_hd__buf_4

sky130 standard-cell layout `sky130_fd_sc_hd__buf_4` from the #4 test corpus.

Schematic

Drawn from PDK netlist `sky130_fd_sc_hd__buf_4.spice` @ commit `ac7fb61f` (google/skywater-pdk-libs-sky130_fd_sc_hd), sha256 `ea462df08556…40d682`. 2 series CMOS inverter stages (10 physical devices: 1+1 for the first stage, 4+4 folded for the drive-boosted second stage) — verified device-by-device in issue #1123's PR body.

Renders

Click a render to open an interactive, pan/zoom viewer of the actual GDS.

Overview render of sky130_fd_sc_hd__buf_4 — Overview

diff.drawing render of sky130_fd_sc_hd__buf_4 — diff.drawing

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li1.drawing render of sky130_fd_sc_hd__buf_4 — li1.drawing

licon1.drawing render of sky130_fd_sc_hd__buf_4 — licon1.drawing

mcon.drawing render of sky130_fd_sc_hd__buf_4 — mcon.drawing

met1.drawing render of sky130_fd_sc_hd__buf_4 — met1.drawing

poly.drawing render of sky130_fd_sc_hd__buf_4 — poly.drawing

Metrics

Layers	22
Cells	1
Instances	0

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Layout (sky130_fd_sc_hd__buf_4.gds)

Schematic

Renders

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