sky130_fd_sc_hd__inv_1

sky130 standard-cell layout `sky130_fd_sc_hd__inv_1` from the #4 test corpus.

Schematic

Hand-drawn 2-transistor CMOS inverter topology, illustrating `sky130_fd_sc_hd__inv_1.gds` (sha256 18a9cfa39995…7914c4). See issue #1123 for netlist-derived standard-cell diagrams.

Renders

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Overview render of sky130_fd_sc_hd__inv_1 — Overview

diff.drawing render of sky130_fd_sc_hd__inv_1 — diff.drawing

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li1.drawing render of sky130_fd_sc_hd__inv_1 — li1.drawing

licon1.drawing render of sky130_fd_sc_hd__inv_1 — licon1.drawing

mcon.drawing render of sky130_fd_sc_hd__inv_1 — mcon.drawing

met1.drawing render of sky130_fd_sc_hd__inv_1 — met1.drawing

poly.drawing render of sky130_fd_sc_hd__inv_1 — poly.drawing

Metrics

Layers	22
Cells	1
Instances	0

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Layout (sky130_fd_sc_hd__inv_1.gds)

Schematic

Renders

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