sky130_fd_sc_hd__nand2_2

sky130 standard-cell layout `sky130_fd_sc_hd__nand2_2` from the #4 test corpus.

Schematic

Drawn from PDK netlist `sky130_fd_sc_hd__nand2_2.spice` @ commit `ac7fb61f` (google/skywater-pdk-libs-sky130_fd_sc_hd), sha256 `90624697a8d4…e1490e`. Classic NAND2 topology (2 series NMOS + 2 parallel PMOS, 8 physical devices, each logical transistor folded x2) — verified device-by-device in issue #1123's PR body.

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Overview render of sky130_fd_sc_hd__nand2_2 — Overview

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Metrics

Layers	22
Cells	1
Instances	0

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Layout (sky130_fd_sc_hd__nand2_2.gds)

Schematic

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